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The continued scaling of integrated circuit fabrication technology will dramatically affect the architecture of future computing systems. Scaling will make computation cheaper, smaller, and lower power, thus enabling more sophisticated computation in a growing number of embedded applications. This spread of low-cost, low power computing can easily be seen in today’s wired (e.g. gigabit Ethernet or DSL) and wireless communication devices, gaming consoles, and handheld PDAs. These new applications have different characteristics from today’s standard workloads, often containing highly data- parallel streaming behavio4r. While the applications will demand ever-growing compute performance, power (ops/W) and computational efficiency (ops/$) are also paramount; therefore, designers have created narrowly focused custom silicon solutions to meet these needs.
Smart Memories Seminar Report
Page Length : 35
- SMART MEMORIES OVERVIEW
- TILE ARCHITECTURE
Smart Memories Presentation Report (PPT)
Page Length : 19
- Packet Processing Workload Challenges
- Solution –Smart Memory
- Introduction to Smart Memory
- Smart Memory Architecture
- Packet Processing Bottlenecks
- Smart Memory
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